High density electronic modules are formed from stacks of integrated circuit carrying chips which are electrically connected and bonded. These stacks are used to provide very densely packed electronic circuitry in a small package to conserve space. A process and apparatus for forming such electronic stacks are described in U.S. Ser. No. 674,096, filed Nov. 23, 1984. The process comprises the steps of measuring the thickness of the chips and placing the chips in an appropriate storage location depending on the thickness characterization of the chips. The chip thickness data is used in a computer program to determine the optimum stacking order of measured chips for a given stack. The chips are cleaned and stacked with a measured quantity of epoxy deposited between the faces of each pair of adjacent chips. Pressure is applied to the stack perpendicularly to the planes of the chips to confine the stack to a predetermined thickness. The epoxy is cured under heat to bond the individual chips into a single stack.
The chips are coated on each upper surface with an excess of adhesive and stacked in the receptacle on the top of the fixture where they are then subjected to compression in the fixture to compress the stack of chips into essentially its final thickness. The fixture is then transferred to an oven and the stack is cured at a temperature ranging from 120.degree. C. to 250.degree. C. for one to three hours, depending upon the adhesive used. After curing the stack is removed from the fixture and processed to remove excess adhesive from the surfaces of the stack. Passivation layers, metal pads, buslines and the like, as may be required by the end use for the stack, are attached following the curing operation.
Such stacks are highly useful in those environments requiring a large amount of electrical circuitry in a small space. For example U.S. Pat. No. 4,525,921 describes the manufacture and the use of stacked circuit carrying chips for general electronic purposes, including computer memory components. U.S. Pat. No. 4,551,629 describes stacked chip modules having a plurality of photo detectors secured to one access plane of the stack to comprise a dense array of radiation/electronic transducers.
Generally an electronic stack comprises in excess of 50 individual circuit carrying chips stacked as described above. However, there is an expanding need for shorter stacks that will fit into a space normally occupied by a single IC chip. The space available can be referred to as "headroom" and "footprint" and in circuit and hardware design this space is often of critical importance. Thus, increasing circuitry without increasing the headroom and footprint of the circuit carrying device is highly desireable. Processing a short stack as an individual item is very difficult in view of the lithography and other processing steps necessary to produce an IC chip stack. Consequently, it is necessary to process a full stack and subsequently segment the stack to produce short stacks. Various methods have been suggested for segmenting a stack of IC chips to form smaller stacks. Segmentation processes involve heating the stack of IC chips to soften the thermoplastic adhesive between the segementation planes after which segments of the desired thickness are removed from the larger stack. This is a labor intensive and time-consuming operation for which, prior to this invention, no practical tool was available.